{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1555258493921 ""} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1555258493927 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 15 00:14:53 2019 " "Processing started: Mon Apr 15 00:14:53 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1555258493927 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1555258493927 ""} { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Timer -c Timer " "Command: quartus_map --read_settings_files=on --write_settings_files=off Timer -c Timer" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1555258493927 ""} { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1555258495011 ""} { "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Only one processor detected - disabling parallel compilation" { } { } 0 20029 "Only one processor detected - disabling parallel compilation" 0 0 "Analysis & Synthesis" 0 -1 1555258495011 ""} { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "timer.v 1 1 " "Found 1 design units, including 1 entities, in source file timer.v" { { "Info" "ISGN_ENTITY_NAME" "1 Timer " "Found entity 1: Timer" { } { { "Timer.v" "" { Text "E:/My_design/Timer/Timer.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1555258523151 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1555258523151 ""} { "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "count Timer.v(57) " "Verilog HDL error at Timer.v(57): object \"count\" is not declared. Verify the object name is correct. If the name is correct, declare the object." { } { { "Timer.v" "" { Text "E:/My_design/Timer/Timer.v" 57 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1555258523167 ""} { "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 1 Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4774 " "Peak virtual memory: 4774 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1555258523276 ""} { "Error" "EQEXE_END_BANNER_TIME" "Mon Apr 15 00:15:23 2019 " "Processing ended: Mon Apr 15 00:15:23 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1555258523276 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:30 " "Elapsed time: 00:00:30" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1555258523276 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1555258523276 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1555258523276 ""} { "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 1 " "Quartus Prime Full Compilation was unsuccessful. 3 errors, 1 warning" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1555258523948 ""}